PoC.xil.reconfig.icap_wrapper

This module was designed to connect the Xilinx “Internal Configuration Access Port” (ICAP) to a PCIe endpoint on a Dini board. Tested on:

tbd

Entity Declaration:

 1  generic (
 2    MIN_DEPTH_OUT     : positive := 256;
 3    MIN_DEPTH_IN      : positive := 256
 4  );
 5  port (
 6    clk       : in  std_logic;
 7    reset     : in  std_logic;
 8    clk_icap    : in  std_logic;    -- clock signal for ICAP, max 100 MHz (double check with manual)
 9
10    icap_busy   : out std_logic;    -- the ICAP is processing the data
11    icap_readback : out std_logic;    -- high during a readback
12    icap_partial_res: out std_logic;    -- high during reconfiguration
13
14    -- data in
15    write_put   : in  std_logic;
16    write_full    : out std_logic;
17    write_data    : in  std_logic_vector(31 downto 0);
18    write_done    : in  std_logic;    -- high pulse/edge after all data was written
19
20    -- data out
21    read_got    : in  std_logic;
22    read_valid    : out std_logic;
23    read_data     : out std_logic_vector(31 downto 0)
24  );
25end reconfig_icap_wrapper;