PoC.xil.BSCAN

This module wraps Xilinx “Boundary Scan” (JTAG) primitives in a generic module.
Supported devices are:

  • Spartan-3, Spartan-6

  • Virtex-5, Virtex-6

  • Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000)

Entity Declaration:

 1  );
 2  port (
 3    Reset               : out std_logic;
 4    RunTest             : out std_logic;
 5    Sel                 : out std_logic;
 6    Capture             : out std_logic;
 7    drck                : out std_logic;
 8    Shift               : out std_logic;
 9    Test_Clock          : out std_logic;
10    Test_DataIn         : out std_logic;
11    Test_DataOut        : in  std_logic;
12    Test_ModeSelect     : out std_logic;
13    Update              : out std_logic
14  );
15end entity;
16
17
18architecture rtl of xil_BSCAN is
19  constant DEV_INFO   : T_DEVICE_INFO := DEVICE_INFO;