PoC.xil.BSCAN

This module wraps Xilinx “Boundary Scan” (JTAG) primitives in a generic module.
Supported devices are:

  • Spartan-3, Spartan-6

  • Virtex-5, Virtex-6

  • Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000)

Entity Declaration:

 1  generic (
 2    JTAG_CHAIN          : natural;
 3    DISABLE_JTAG        : boolean     := FALSE
 4  );
 5  port (
 6    Reset               : out std_logic;
 7    RunTest             : out std_logic;
 8    Sel                 : out std_logic;
 9    Capture             : out std_logic;
10    drck                : out std_logic;
11    Shift               : out std_logic;
12    Test_Clock          : out std_logic;
13    Test_DataIn         : out std_logic;
14    Test_DataOut        : in  std_logic;
15    Test_ModeSelect     : out std_logic;
16    Update              : out std_logic
17  );
18end entity;