PoC.xil.ICAP

This module wraps Xilinx “Internal Configuration Access Port” (ICAP) primitives in a generic module.
Supported devices are:

  • Spartan-6

  • Virtex-4, Virtex-5, Virtex-6

  • Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000)

Entity Declaration:

 1  generic (
 2    ICAP_WIDTH  : string := "X32";          -- Specifies the input and output data width to be used
 3                              -- Spartan 6: fixed to 16 bit
 4                              -- Virtex 4:  X8 or X32
 5                              -- Rest: X8, X16, X32
 6    DEVICE_ID : bit_vector := X"1234567";       -- pre-programmed Device ID value for simulation
 7                              -- supported by Spartan 6, Virtex 6 and above
 8    SIM_CFG_FILE_NAME : string  := "NONE"     -- Raw Bitstream (RBT) file to be parsed by the simulation model
 9                              -- supported by Spartan 6, Virtex 6 and above
10  );
11  port (
12    clk     : in std_logic;           -- up to 100 MHz (Virtex-6 and above, Virtex-5??)
13    disable   : in std_logic;           -- low active enable -> high active disable
14    rd_wr   : in std_logic;           -- 0 - write, 1 - read
15    busy    : out std_logic;            -- on Series-7 devices always '0'
16    data_in   : in std_logic_vector(31 downto 0); -- on Spartan-6 only 15 downto 0
17    data_out  : out std_logic_vector(31 downto 0) -- on Spartan-6 only 15 downto 0
18  );
19end entity;