PoC.xil.ICAP

This module wraps Xilinx “Internal Configuration Access Port” (ICAP) primitives in a generic module.
Supported devices are:

  • Spartan-6

  • Virtex-4, Virtex-5, Virtex-6

  • Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000)

Entity Declaration:

 1                              -- Virtex 4:  X8 or X32
 2                              -- Rest: X8, X16, X32
 3    DEVICE_ID  :  bit_vector := X"1234567";        -- pre-programmed Device ID value for simulation
 4                              -- supported by Spartan 6, Virtex 6 and above
 5    SIM_CFG_FILE_NAME  : string  := "NONE"      -- Raw Bitstream (RBT) file to be parsed by the simulation model
 6                              -- supported by Spartan 6, Virtex 6 and above
 7  );
 8  port (
 9    Clock      : in  std_logic;            -- up to 100 MHz (Virtex-6 and above, Virtex-5??)
10    Disable    : in  std_logic;            -- low active enable -> high active disable
11    ReadWrite  : in  std_logic;            -- 0 - write, 1 - read
12    Busy      : out std_logic;            -- on Series-7 devices always '0'
13    DataIn    : in  std_logic_vector(31 downto 0);  -- on Spartan-6 only 15 downto 0
14    DataOut    : out std_logic_vector(31 downto 0)  -- on Spartan-6 only 15 downto 0
15  );
16end entity;
17
18
19architecture rtl of xil_ICAP is
20  constant DEV_INFO    : T_DEVICE_INFO  := DEVICE_INFO;