PoC.xil.Reconfigurator
Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration Port (DRP) to reconfigure a primitive at runtime without reconfiguring the whole FPGA.
This module is a DRP master that can be pre-configured at compile time with
different configuration sets. The configuration sets are mapped into a ROM.
The user can select a stored configuration with ConfigSelect. Sending a
strobe to Reconfig will start the reconfiguration process. The operation
completes with another strobe on ReconfigDone.
Entity Declaration:
1 generic (
2 DEBUG : boolean := FALSE; --
3 CLOCK_FREQ : FREQ := 100 MHz; --
4 CONFIG_ROM : in T_XIL_DRP_CONFIG_ROM := (0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY) --
5 );
6 port (
7 Clock : in std_logic;
8 Reset : in std_logic;
9
10 Reconfig : in std_logic; --
11 ReconfigDone : out std_logic; --
12 ConfigSelect : in std_logic_vector(log2ceilnz(CONFIG_ROM'length) - 1 downto 0); --
13
14 DRP_en : out std_logic; --
15 DRP_Address : out T_XIL_DRP_ADDRESS; --
16 DRP_we : out std_logic; --
17 DRP_DataIn : in T_XIL_DRP_DATA; --
18 DRP_DataOut : out T_XIL_DRP_DATA; --
19 DRP_Ack : in std_logic --
20 );
21end entity;