PoC.xil.Reconfigurator

Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration Port (DRP) to reconfigure a primitive at runtime without reconfiguring the whole FPGA.

This module is a DRP master that can be pre-configured at compile time with different configuration sets. The configuration sets are mapped into a ROM. The user can select a stored configuration with ConfigSelect. Sending a strobe to Reconfig will start the reconfiguration process. The operation completes with another strobe on ReconfigDone.

Entity Declaration:

 1    CONFIG_ROM      : in  T_XIL_DRP_CONFIG_ROM  := (0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY)   --
 2  );
 3  port (
 4    Clock           : in  std_logic;
 5    Reset           : in  std_logic;
 6
 7    Reconfig        : in  std_logic;                                                            --
 8    ReconfigDone    : out std_logic;                                                            --
 9    ConfigSelect    : in  std_logic_vector(log2ceilnz(CONFIG_ROM'length) - 1 downto 0);         --
10
11    DRP_en          : out std_logic;                                                            --
12    DRP_Address     : out T_XIL_DRP_ADDRESS;                                                    --
13    DRP_we          : out std_logic;                                                            --
14    DRP_DataIn      : in  T_XIL_DRP_DATA;                                                       --
15    DRP_DataOut     : out T_XIL_DRP_DATA;                                                       --
16    DRP_Ack         : in  std_logic                                                             --
17  );
18end entity;
19
20
21architecture rtl of xil_Reconfigurator is
22  attribute KEEP                : boolean;