.. _IP:reconfig_icap_wrapper:

PoC.xil.reconfig.icap_wrapper
#############################

.. only:: html

   .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png
               :scale: 40
               :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/reconfig/reconfig_icap_wrapper.vhdl
               :alt: Source Code on GitHub
   .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png
               :scale: 40
               :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/xil/reconfig/reconfig_icap_wrapper_tb.vhdl
               :alt: Source Code on GitHub

   .. sidebar:: GitHub Links

      * |gh-src| :pocsrc:`Sourcecode <xil/reconfig/reconfig_icap_wrapper.vhdl>`
      * |gh-tb| :poctb:`Testbench <xil/reconfig/reconfig_icap_wrapper_tb.vhdl>`

This module was designed to connect the Xilinx "Internal Configuration Access Port" (ICAP)
to a PCIe endpoint on a Dini board. Tested on:

tbd



.. rubric:: Entity Declaration:

.. literalinclude:: ../../../../src/xil/reconfig/reconfig_icap_wrapper.vhdl
   :language: vhdl
   :tab-width: 2
   :linenos:
   :lines: 43-68



.. only:: latex

   Source file: :pocsrc:`xil/reconfig/reconfig_icap_wrapper.vhdl <xil/reconfig/reconfig_icap_wrapper.vhdl>`