PoC.xil.reconfig.icap_fsm

This module parses the data stream to the Xilinx “Internal Configuration Access Port” (ICAP) primitives to generate control signals. Tested on:

  • Virtex-6

  • Virtex-7

Entity Declaration:

 1  port  (
 2    clk       : in  std_logic;
 3    reset     : in  std_logic;            -- high-active reset
 4    -- interface to connect to the icap
 5    icap_in     : out std_logic_vector(31 downto 0);  -- data that will go into the icap
 6    icap_out    : in  std_logic_vector(31 downto 0);  -- data from the icap
 7    icap_csb    : out std_logic;
 8    icap_rw     : out std_logic;
 9
10    -- data interface, no internal fifos
11    in_data     : in  std_logic_vector(31 downto 0);  -- new configuration data
12    in_data_valid : in  std_logic;            -- input data is valid
13    in_data_rden  : out std_logic;            -- possible to send data
14    out_data    : out std_logic_vector(31 downto 0);  -- data read from the fifo
15    out_data_valid  : out std_logic;            -- data from icap is valid
16    out_data_full : in  std_logic;            -- receiving buffer is full, halt icap
17
18    -- control structures
19    status      : out std_logic_vector(31 downto 0) -- status vector
20  );
21end reconfig_icap_fsm;