PoC.fifo.Stage

Its primary use is the decoupling of enable domains in a processing pipeline. Data storage is limited to two words only so as to allow both the ful and the vld indicators to be driven by registers.

Entity Declaration:

 1  generic (
 2    D_BITS       : positive;
 3    STAGES       : natural := 1;    -- 0 creates a passthrough, all values above creates one pipeline stage of the set depth
 4    LIGHT_WEIGHT : boolean := FALSE -- This option uses half of registers but oszilates between full and empty! Use only when restriction is acceptable (e.g. for Address channel in AXI)
 5  );
 6  port (
 7    -- Control
 8    clk : in  std_logic; -- Clock
 9    rst : in  std_logic; -- Synchronous Reset
10
11    -- Input
12    put : in  std_logic;                             -- Put Value
13    di  : in  std_logic_vector(D_BITS - 1 downto 0); -- Data Input
14    ful : out std_logic;                             -- Full
15
16    -- Output
17    vld : out std_logic;                             -- Data Available
18    do  : out std_logic_vector(D_BITS - 1 downto 0); -- Data Output
19    got : in  std_logic                              -- Data Consumed
20  );