PoC.fifo.ic_got

Independent clocks meens that read and write clock are unrelated.

This implementation uses dedicated block RAM for storing data.

First-word-fall-through (FWFT) mode is implemented, so data can be read out as soon as valid goes high. After the data has been captured, then the signal got must be asserted.

Synchronous reset is used. Both resets may overlap.

DATA_REG (=true) is a hint, that distributed memory or registers should be used as data storage. The actual memory type depends on the device architecture. See implementation for details.

*STATE_*_BITS defines the granularity of the fill state indicator *State. FillState is associated with the read clock domain and outputs the guaranteed number of words available in the FIFO. EmptyState is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the full or valid outputs as they may be implemented as giving pessimistic bounds that are minimally off the true fill state.

If a fill state is not of interest, set *STATE_*_BITS = 0.

FillState and EmptyState are combinatorial outputs and include an address comparator (subtractor) in their path.

Examples: - FILL_STATE_BITS = 1: FillState == 0 => 0/2 full

FillState == 1 => 1/2 full (half full)

  • FILL_STATE_BITS = 2: FillState == 0 => 0/4 full

    FillState == 1 => 1/4 full FillState == 2 => 2/4 full FillState == 3 => 3/4 full

Entity Declaration:

 1    DATA_BITS      : positive;          -- Data Width
 2    MIN_DEPTH      : positive;          -- Minimum FIFO Depth
 3    DATA_REG       : boolean := false;  -- Store Data Content in Registers
 4    OUTPUT_REG     : boolean := false;  -- Registered FIFO Output
 5    EMPTY_STATE_BITS : natural := 0;      -- Empty State Bits
 6    FILL_STATE_BITS  : natural := 0       -- Full State Bits
 7  );
 8  port (
 9    -- Write Interface
10    Write_Clock      : in  std_logic;
11    Write_Reset      : in  std_logic;
12    Write_Put        : in  std_logic;
13    Write_DataIn     : in  std_logic_vector(DATA_BITS-1 downto 0);
14    Write_Full       : out std_logic;
15    Write_EmptyState : out std_logic_vector(imax(EMPTY_STATE_BITS-1, 0) downto 0);
16
17    -- Read Interface
18    Read_Clock     : in  std_logic;
19    Read_Reset     : in  std_logic;
20    Read_Valid     : out std_logic;
21    Read_DataOut   : out std_logic_vector(DATA_BITS-1 downto 0);
22    Read_Got       : in  std_logic;
23    Read_FillState : out std_logic_vector(imax(FILL_STATE_BITS-1, 0) downto 0)
24  );
25end entity;