PoC.fifo.cc_got

This module implements a regular FIFO with common clock (cc), pipelined interface. Common clock means read and write port use the same clock. The FIFO size can be configured in word width (D_BITS) and minimum word count MIN_DEPTH. The specified depth is rounded up to the next suitable value.

DATA_REG (=true) is a hint, that distributed memory or registers should be used as data storage. The actual memory type depends on the device architecture. See implementation for details.

*STATE_*_BITS defines the granularity of the fill state indicator *state_*. If a fill state is not of interest, set *STATE_*_BITS = 0. fstate_rd is associated with the read clock domain and outputs the guaranteed number of words available in the FIFO. estate_wr is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the full or valid outputs as they may be implemented as giving pessimistic bounds that are minimally off the true fill state.

fstate_rd and estate_wr are combinatorial outputs and include an address comparator (subtractor) in their path.

Examples:

  • FSTATE_RD_BITS = 1:

    fstate_rd

    filled (at least)

    0

    0/2 full

    1

    1/2 full (half full)

  • FSTATE_RD_BITS = 2:

    fstate_rd

    filled (at least)

    0

    0/4 full

    1

    1/4 full

    2

    2/4 full (half full)

    3

    3/4 full

Entity Declaration:

 1    D_BITS          : positive; -- Data Width
 2    MIN_DEPTH       : positive; -- Minimum FIFO Depth
 3    RAM_TYPE        : T_RAM_TYPE := RAM_TYPE_OPTIMIZED;
 4    DATA_REG        : boolean    := false; -- Store Data Content in Registers
 5    LUT_SHIFT_LOGIC : boolean    := false; -- Store Data Content in Lut-Shift-Logic (only possible in Xilinx devices)
 6    STATE_REG       : boolean    := false; -- Registered Full/Empty Indicators
 7    OUTPUT_REG      : boolean    := false; -- Registered FIFO Output
 8    ESTATE_WR_BITS  : natural    := 0;     -- Empty State Bits
 9    FSTATE_RD_BITS  : natural    := 0      -- Full State Bits
10  );
11  port (
12    -- Global Reset and Clock
13    rst, clk : in std_logic;
14
15    -- Writing Interface
16    put       : in std_logic;                             -- Write Request
17    din       : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
18    full      : out std_logic;
19    estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
20
21    -- Reading Interface
22    got       : in std_logic;                              -- Read Completed
23    dout      : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
24    valid     : out std_logic;
25    fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)
26  );
27end entity fifo_cc_got;

See also

IP/fifo_dc_got

For a FIFO with dependent clocks.

PoC.fifo.ic_got

For a FIFO with independent clocks (cross-clock FIFO).

IP/fifo_glue

For a minimal FIFO / pipeline decoupling.