PoC.fifo.shift

This FIFO implementation is based on an internal shift register. This is especially useful for smaller FIFO sizes, which can be implemented in LUT storage on some devices (e.g. Xilinx’ SRLs). Only a single read pointer is maintained, which determines the number of valid entries within the underlying shift register.

The specified depth (MIN_DEPTH) is rounded up to the next suitable value.

Entity Declaration:

 1  generic (
 2    D_BITS    : positive;               -- Data Width
 3    MIN_DEPTH : positive                -- Minimum FIFO Size in Words
 4  );
 5  port (
 6    -- Global Control
 7    clk  : in  std_logic;
 8    rst  : in  std_logic;
 9    fill : out std_logic_vector(log2ceilnz(MIN_DEPTH) downto 0); -- Fill'left = Empty, Fill'left = no vld
10                                                                 -- If vld='1' then fill(fill'left -1 downto 0) +1 is the number of Words saved
11
12    -- Writing Interface
13    put  : in  std_logic;                            -- Write Request
14    din  : in  std_logic_vector(D_BITS-1 downto 0);  -- Input Data
15    ful  : out std_logic;                            -- Capacity Exhausted
16
17    -- Reading Interface
18    got  : in  std_logic;                            -- Read Done Strobe
19    dout : out std_logic_vector(D_BITS-1 downto 0);  -- Output Data
20    vld  : out std_logic                             -- Data Valid
21  );