PoC.fifo.shift

This FIFO implementation is based on an internal shift register. This is especially useful for smaller FIFO sizes, which can be implemented in LUT storage on some devices (e.g. Xilinx’ SRLs). Only a single read pointer is maintained, which determines the number of valid entries within the underlying shift register.

The specified depth (MIN_DEPTH) is rounded up to the next suitable value.

Entity Declaration:

 1  generic (
 2    D_BITS    : positive;               -- Data Width
 3    MIN_DEPTH : positive                -- Minimum FIFO Size in Words
 4  );
 5  port (
 6    -- Global Control
 7    clk : in std_logic;
 8    rst : in std_logic;
 9
10    -- Writing Interface
11    put : in  std_logic;                            -- Write Request
12    din : in  std_logic_vector(D_BITS-1 downto 0);  -- Input Data
13    ful : out std_logic;                            -- Capacity Exhausted
14
15    -- Reading Interface
16    got  : in  std_logic;                            -- Read Done Strobe
17    dout : out std_logic_vector(D_BITS-1 downto 0);  -- Output Data
18    vld  : out std_logic                             -- Data Valid
19  );
20end entity fifo_shift;