PoC.fifo.cc_got_tempgot

The specified depth (MIN_DEPTH) is rounded up to the next suitable value.

As uncommitted reads occupy FIFO space that is not yet available for writing, an instance of this FIFO can, indeed, report full and not vld at the same time. While a commit would eventually make space available for writing (not ful), a rollback would re-iterate data for reading (vld).

commit and rollback are inclusive and apply to all reads (got) since the previous commit or rollback up to and including a potentially simultaneous read.

The FIFO state upon a simultaneous assertion of commit and rollback is undefined!

*STATE_*_BITS defines the granularity of the fill state indicator *state_*. fstate_rd is associated with the read clock domain and outputs the guaranteed number of words available in the FIFO. estate_wr is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the full or valid outputs as they may be implemented as giving pessimistic bounds that are minimally off the true fill state.

If a fill state is not of interest, set *STATE_*_BITS = 0.

fstate_rd and estate_wr are combinatorial outputs and include an address comparator (subtractor) in their path.

Examples:

  • FSTATE_RD_BITS = 1:

    • fstate_rd == 0 => 0/2 full

    • fstate_rd == 1 => 1/2 full (half full)

  • FSTATE_RD_BITS = 2:

    • fstate_rd == 0 => 0/4 full

    • fstate_rd == 1 => 1/4 full

    • fstate_rd == 2 => 2/4 full

    • fstate_rd == 3 => 3/4 full

Entity Declaration:

 1  generic (
 2    D_BITS         : positive;          -- Data Width
 3    MIN_DEPTH      : positive;          -- Minimum FIFO Depth
 4    DATA_REG       : boolean := false;  -- Store Data Content in Registers
 5    STATE_REG      : boolean := false;  -- Registered Full/Empty Indicators
 6    OUTPUT_REG     : boolean := false;  -- Registered FIFO Output
 7    ESTATE_WR_BITS : natural := 0;      -- Empty State Bits
 8    FSTATE_RD_BITS : natural := 0       -- Full State Bits
 9  );
10  port (
11    -- Global Reset and Clock
12    rst, clk : in  std_logic;
13
14    -- Writing Interface
15    put       : in  std_logic;                            -- Write Request
16    din       : in  std_logic_vector(D_BITS-1 downto 0);  -- Input Data
17    full      : out std_logic;
18    estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
19
20    -- Reading Interface
21    got       : in  std_logic;                            -- Read Completed
22    dout      : out std_logic_vector(D_BITS-1 downto 0);  -- Output Data
23    valid     : out std_logic;
24    fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0);
25
26    commit    : in  std_logic;
27    rollback  : in  std_logic
28  );
29end entity fifo_cc_got_tempgot;