PoC.fifo.cc_got_tempput

The specified depth (MIN_DEPTH) is rounded up to the next suitable value.

As uncommitted writes populate FIFO space that is not yet available for reading, an instance of this FIFO can, indeed, report full and not vld at the same time. While a commit would eventually make data available for reading (vld), a rollback would free the space for subsequent writing (not ful).

commit and rollback are inclusive and apply to all writes (put) since the previous ‘commit’ or ‘rollback’ up to and including a potentially simultaneous write.

The FIFO state upon a simultaneous assertion of commit and rollback is undefined.

*STATE_*_BITS defines the granularity of the fill state indicator *state_*. fstate_rd is associated with the read clock domain and outputs the guaranteed number of words available in the FIFO. estate_wr is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the full or valid outputs as they may be implemented as giving pessimistic bounds that are minimally off the true fill state.

If a fill state is not of interest, set *STATE_*_BITS = 0.

fstate_rd and estate_wr are combinatorial outputs and include an address comparator (subtractor) in their path.

Examples:

  • FSTATE_RD_BITS = 1:

    • fstate_rd == 0 => 0/2 full

    • fstate_rd == 1 => 1/2 full (half full)

  • FSTATE_RD_BITS = 2:

    • fstate_rd == 0 => 0/4 full

    • fstate_rd == 1 => 1/4 full

    • fstate_rd == 2 => 2/4 full

    • fstate_rd == 3 => 3/4 full

Entity Declaration:

 1entity fifo_cc_got_tempput is
 2  generic (
 3    RAM_TYPE       : T_RAM_TYPE := RAM_TYPE_OPTIMIZED;--RAM_TYPE_AUTO;     
 4    D_BITS         : positive;         -- Data Width
 5    MIN_DEPTH      : positive;         -- Minimum FIFO Depth
 6    DATA_REG       : boolean := false; -- Store Data Content in Registers
 7    STATE_REG      : boolean := false; -- Registered Full/Empty Indicators
 8    OUTPUT_REG     : boolean := false; -- Registered FIFO Output
 9    ESTATE_WR_BITS : natural := 0;     -- Empty State Bits
10    FSTATE_RD_BITS : natural := 0      -- Full State Bits
11  );
12  port (
13    -- Global Reset and Clock
14    rst, clk : in std_logic;
15
16    -- Writing Interface
17    put       : in std_logic;                             -- Write Request
18    din       : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
19    full      : out std_logic;
20    estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
21
22    commit   : in std_logic;
23    rollback : in std_logic;
24
25    -- Reading Interface
26    got       : in std_logic;                              -- Read Completed
27    dout      : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
28    valid     : out std_logic;
29    fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)