PoC.xil.reconfig.ICAP_Wrapper

This module was designed to connect the Xilinx “Internal Configuration Access Port” (ICAP) to a PCIe endpoint on a Dini board. Tested on:

tbd

Entity Declaration:

 1  );
 2  port (
 3    Clock            : in  std_logic;
 4    Reset            : in  std_logic;
 5    ICAP_Clock       : in  std_logic;    -- clock signal for ICAP, max 100 MHz (double check with manual)
 6
 7    ICAP_Busy        : out std_logic;    -- the ICAP is processing the data
 8    ICAP_Readback    : out std_logic;    -- high during a readback
 9    ICAP_Partial_res : out std_logic;    -- high during reconfiguration
10
11    -- data in
12    Write_Put        : in  std_logic;
13    Write_Data       : in  std_logic_vector(31 downto 0);
14    Write_Full       : out std_logic;
15    Write_Done       : in  std_logic;    -- high pulse/edge after all data was written
16
17    -- data out
18    Read_Valid       : out std_logic;
19    Read_Data        : out std_logic_vector(31 downto 0);
20    Read_Got         : in  std_logic
21  );
22end entity;
23
24architecture Behavioral of reconfig_ICAP_Wrapper is
25  signal reset_icap        : std_logic;