PoC.xil.reconfig.ICAP_FSM

This module parses the data stream to the Xilinx “Internal Configuration Access Port” (ICAP) primitives to generate control signals. Tested on:

  • Virtex-6

  • Virtex-7

Entity Declaration:

 1    -- interface to connect to the icap
 2    icap_in      : out std_logic_vector(31 downto 0);  -- data that will go into the icap
 3    icap_out    : in  std_logic_vector(31 downto 0);  -- data from the icap
 4    icap_csb    : out std_logic;
 5    icap_rw      : out std_logic;
 6
 7    -- data interface, no internal fifos
 8    in_data      : in  std_logic_vector(31 downto 0);  -- new configuration data
 9    in_data_valid  : in  std_logic;            -- input data is valid
10    in_data_rden  : out std_logic;            -- possible to send data
11    out_data    : out std_logic_vector(31 downto 0);  -- data read from the fifo
12    out_data_valid  : out std_logic;            -- data from icap is valid
13    out_data_full  : in  std_logic;            -- receiving buffer is full, halt icap
14
15    -- control structures
16    status      : out std_logic_vector(31 downto 0)  -- status vector
17  );
18end entity;
19
20architecture arch of reconfig_ICAP_FSM is
21
22  type t_state is (ready, abort0, abort1, abort2, abort3, write, writing, pre_reg_read0, pre_reg_read1, pre_stream_read0, read, reading, post_read);