PoC.arith.prng

This module implementes a Pseudo-Random Number Generator (PRNG) with configurable bit count (BITS). This module uses an internal list of FPGA optimized polynomials from 3 to 168 bits. The polynomials have at most 5 tap positions, so that long shift registers can be inferred instead of single flip-flops.

The generated number sequence includes the value all-zeros, but not all-ones.

Entity Declaration:

 1entity arith_prng is
 2    generic (
 3        BITS : positive;
 4    SEED : std_logic_vector := "0"
 5    );
 6    port (
 7        Clock : in std_logic;
 8        Reset : in std_logic; -- reset value to seed
 9
10        InitialValue : in std_logic_vector := SEED; -- Is loaded when Reset = '1'