PoC.arith.addw

Implements wide addition providing several options all based on an adaptation of a carry-select approach.

References:

  • Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, FPL 2011. -> ARCH: AAM, CAI, CCA -> SKIPPING: CCC

  • Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: A Novel Modular Adder for One Thousand Bits and More Using Fast Carry Chains of Modern FPGAs, FPL 2014. -> ARCH: PAI -> SKIPPING: PPN_KS, PPN_BK

Entity Declaration:

 1use     work.arith.all;
 2
 3
 4entity arith_addw is
 5  generic (
 6    N : positive;                    -- Operand Width
 7    K : positive;                    -- Block Count
 8
 9    ARCH        : tArch     := AAM;        -- Architecture
10    BLOCKING    : tBlocking := DFLT;       -- Blocking Scheme
11    SKIPPING    : tSkipping := CCC;        -- Carry Skip Scheme
12    P_INCLUSIVE : boolean   := false       -- Use Inclusive Propagate, i.e. c^1
13  );
14  port (
15    a, b : in std_logic_vector(N-1 downto 0);
16    cin  : in std_logic;
17
18    s    : out std_logic_vector(N-1 downto 0);