PoC.arith.addw

Implements wide addition providing several options all based on an adaptation of a carry-select approach.

References:

  • Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, FPL 2011. -> ARCH: AAM, CAI, CCA -> SKIPPING: CCC

  • Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: A Novel Modular Adder for One Thousand Bits and More Using Fast Carry Chains of Modern FPGAs, FPL 2014. -> ARCH: PAI -> SKIPPING: PPN_KS, PPN_BK

Entity Declaration:

 1entity arith_addw is
 2  generic (
 3    N : positive;                    -- Operand Width
 4    K : positive;                    -- Block Count
 5
 6    ARCH        : tArch     := AAM;        -- Architecture
 7    BLOCKING    : tBlocking := DFLT;       -- Blocking Scheme
 8    SKIPPING    : tSkipping := CCC;        -- Carry Skip Scheme
 9    P_INCLUSIVE : boolean   := false       -- Use Inclusive Propagate, i.e. c^1
10  );
11  port (
12    a, b : in std_logic_vector(N-1 downto 0);
13    cin  : in std_logic;
14
15    s    : out std_logic_vector(N-1 downto 0);
16    cout : out std_logic
17  );
18end entity;