PoC.arith.counter_bcd

Counter with output in binary coded decimal (BCD). The number of BCD digits is configurable by DIGITS.

All control signals (reset rst, increment inc) are high-active and synchronous to clock clk. The output val is the current counter state. Groups of 4 bit represent one BCD digit. The lowest significant digit is specified by val(3 downto 0).

Todo

  • implement a dec input for decrementing

  • implement a load input to load a value

Entity Declaration:

 1  port (
 2    clk : in  std_logic;
 3    rst : in  std_logic;                        -- Reset to 0
 4    inc : in  std_logic;                        -- Increment
 5    val : out T_BCD_VECTOR(DIGITS-1 downto 0)   -- Value output
 6  );
 7end entity;
 8
 9
10architecture rtl of arith_counter_bcd is
11  -- c(i) = carry-in of stage 'i'