PoC.mem.ocram.tdp_wf

Inferring / instantiating true dual-port memory, with:

  • single clock, clock enable,

  • 2 read/write ports.

Command truth table:

ce

we1

we2

Command

0

X

X

No operation

1

0

0

Read only from memory

1

0

1

Read from memory on port 1, write to memory on port 2

1

1

0

Write to memory on port 1, read from memory on port 2

1

1

1

Write to memory on both ports

Both reads and writes are synchronous to the clock.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

Same-Port Read-During-Write

When writing data through port 1, the read output of the same port (q1) will output the new data (d1, in the following clock cycle) which is aka. “write-first behavior”.

Same applies to port 2.

Mixed-Port Read-During-Write

When reading at the write address, the read value will be the new data, aka. “write-first behavior”. Of course, the read is still synchronous, i.e, the latency is still one clock cyle.

If a write is issued on both ports to the same address, then the output of this unit and the content of the addressed memory cell are undefined.

For simulation, always our dedicated simulation model PoC.mem.ocram.tdp_sim is used.

Entity Declaration:

 1  generic (
 2    A_BITS    : positive;                             -- number of address bits
 3    D_BITS    : positive;                             -- number of data bits
 4    FILENAME  : string    := ""                       -- file-name for RAM initialization
 5  );
 6  port (
 7    clk : in  std_logic;                              -- clock
 8    ce  : in  std_logic;                              -- clock-enable
 9    we1 : in  std_logic;                              -- write-enable for 1st port
10    we2 : in  std_logic;                              -- write-enable for 2nd port
11    a1   : in unsigned(A_BITS-1 downto 0);            -- address for 1st port
12    a2   : in unsigned(A_BITS-1 downto 0);            -- address for 2nd port
13    d1   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 1st port
14    d2   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 2nd port
15    q1   : out std_logic_vector(D_BITS-1 downto 0);   -- read-data from 1st port
16    q2   : out std_logic_vector(D_BITS-1 downto 0)    -- read-data from 2nd port
17  );
18end entity;