PoC.mem.ocram.tdp_sim

Simulation model for true dual-port memory, with:

  • dual clock, clock enable,

  • 2 read/write ports.

The interface matches that of the IP core PoC.mem.ocram.tdp. But the implementation there is restricted to the description supported by various synthesis compilers. The implementation here also simulates the correct Mixed-Port Read-During-Write Behavior and handles X propagation.

Entity Declaration:

 1    FILENAME  : string    := ""                       -- file-name for RAM initialization
 2  );
 3  port (
 4    clk1 : in std_logic;                              -- clock for 1st port
 5    clk2 : in std_logic;                              -- clock for 2nd port
 6    ce1 : in  std_logic;                              -- clock-enable for 1st port
 7    ce2 : in  std_logic;                              -- clock-enable for 2nd port
 8    we1 : in  std_logic;                              -- write-enable for 1st port
 9    we2 : in  std_logic;                              -- write-enable for 2nd port
10    a1   : in unsigned(A_BITS-1 downto 0);            -- address for 1st port
11    a2   : in unsigned(A_BITS-1 downto 0);            -- address for 2nd port
12    d1   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 1st port
13    d2   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 2nd port
14    q1   : out std_logic_vector(D_BITS-1 downto 0);   -- read-data from 1st port
15    q2   : out std_logic_vector(D_BITS-1 downto 0)    -- read-data from 2nd port
16  );
17end entity;
18
19
20architecture sim of ocram_tdp_sim is
21  constant DEPTH : positive := 2**A_BITS;