PoC.mem.ocram.tdp_sim

Simulation model for true dual-port memory, with:

  • dual clock, clock enable,

  • 2 read/write ports.

The interface matches that of the IP core PoC.mem.ocram.tdp. But the implementation there is restricted to the description supported by various synthesis compilers. The implementation here also simulates the correct Mixed-Port Read-During-Write Behavior and handles X propagation.

Entity Declaration:

 1  generic (
 2    A_BITS    : positive;                             -- number of address bits
 3    D_BITS    : positive;                             -- number of data bits
 4    FILENAME  : string    := ""                       -- file-name for RAM initialization
 5  );
 6  port (
 7    clk1 : in std_logic;                              -- clock for 1st port
 8    clk2 : in std_logic;                              -- clock for 2nd port
 9    ce1 : in  std_logic;                              -- clock-enable for 1st port
10    ce2 : in  std_logic;                              -- clock-enable for 2nd port
11    we1 : in  std_logic;                              -- write-enable for 1st port
12    we2 : in  std_logic;                              -- write-enable for 2nd port
13    a1   : in unsigned(A_BITS-1 downto 0);            -- address for 1st port
14    a2   : in unsigned(A_BITS-1 downto 0);            -- address for 2nd port
15    d1   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 1st port
16    d2   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 2nd port
17    q1   : out std_logic_vector(D_BITS-1 downto 0);   -- read-data from 1st port
18    q2   : out std_logic_vector(D_BITS-1 downto 0)    -- read-data from 2nd port
19  );
20end entity;