PoC.mem.ocram.sdp_wf

Inferring / instantiating simple dual-port memory, with:

  • single clock, clock enable,

  • 1 read port plus 1 write port.

Command truth table:

ce

we

Command

0

X

No operation

1

0

Read only from memory

1

1

Read from and Write to memory

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

Mixed-Port Read-During-Write

When reading at the write address, the read value will be the new data, aka. “write-first behavior”. Of course, the read is still synchronous, i.e, the latency is still one clock cyle.

Entity Declaration:

 1    D_BITS    : positive;                           -- number of data bits
 2    FILENAME  : string    := ""                     -- file-name for RAM initialization
 3  );
 4  port (
 5    clk : in  std_logic;                            -- clock
 6    ce  : in  std_logic;                            -- clock-enable
 7    we  : in  std_logic;                            -- write enable
 8    ra  : in  unsigned(A_BITS-1 downto 0);          -- read address
 9    wa  : in  unsigned(A_BITS-1 downto 0);          -- write address
10    d   : in  std_logic_vector(D_BITS-1 downto 0);  -- data in
11    q   : out std_logic_vector(D_BITS-1 downto 0)   -- data out
12  );
13end entity;
14
15
16architecture rtl of ocram_sdp_wf is