PoC.io.uart.FIFO

Small FIFO s are included in this module, if larger or asynchronous transmit / receive FIFOs are required, then they must be connected externally.

old comments:

UART BAUD rate generator bclk = bit clock is rising bclk_x8 = bit clock times 8 is rising

Entity Declaration:

 1entity uart_FIFO is
 2  generic (
 3    -- Communication Parameters
 4    CLOCK_FREQ                      : FREQ;
 5    BAUDRATE                        : BAUD;
 6    PARITY                          : T_UART_PARITY_MODE           := PARITY_NONE;
 7    PARITY_ERROR_HANDLING           : T_UART_PARITY_ERROR_HANDLING := PASSTHROUGH_ERROR_BYTE;
 8    PARITY_ERROR_IDENTIFIER         : std_logic_vector(7 downto 0) := 8x"0";
 9    ADD_INPUT_SYNCHRONIZERS         : boolean := TRUE;
10
11    -- Buffer Dimensioning
12    TX_MIN_DEPTH                    : positive          := 16;
13    TX_EMPTY_STATE_BITS             : natural           := 0;     -- XXX: adjust to FIFO naming
14    RX_MIN_DEPTH                    : positive          := 16;
15    RX_FILL_STATE_BITS              : natural           := 0;
16
17    FLOWCTRL_XON_THRESHOLD          : real := 0.0625;
18    FLOWCTRL_XOFF_THRESHOLD         : real := 0.75;
19
20    -- Flow Control
21    FLOWCONTROL                     : T_UART_FLOWCONTROL_KIND   := UART_FLOWCONTROL_NONE;
22    SWFC_XON_CHAR                   : std_logic_vector(7 downto 0) := x"11";  -- ^Q
23
24    SWFC_XOFF_CHAR                  : std_logic_vector(7 downto 0) := x"13"   -- ^S
25  );
26  port (
27    Clock               : in  std_logic;
28    Reset               : in  std_logic;
29
30    -- FIFO interface
31    TX_Put              : in  std_logic;
32    TX_Data             : in  std_logic_vector(7 downto 0);
33    TX_Full             : out std_logic;
34    TX_EmptyState       : out std_logic_vector(imax(0, TX_EMPTY_STATE_BITS-1) downto 0);
35    TXFIFO_Reset        : in  std_logic;
36    TXFIFO_Empty        : out std_logic;
37
38    RX_Valid            : out std_logic;
39    RX_Data             : out std_logic_vector(7 downto 0);
40    RX_Got              : in  std_logic;
41    RX_FillState        : out std_logic_vector(imax(0, RX_FILL_STATE_BITS-1) downto 0);
42    RX_Overflow         : out std_logic;
43    RXFIFO_Full         : out std_logic;