PoC.io.uart.fifo

Small FIFO s are included in this module, if larger or asynchronous transmit / receive FIFOs are required, then they must be connected externally.

old comments:

UART BAUD rate generator bclk = bit clock is rising bclk_x8 = bit clock times 8 is rising

Entity Declaration:

 1entity uart_fifo is
 2  generic (
 3    -- Communication Parameters
 4    CLOCK_FREQ                      : FREQ;
 5    BAUDRATE                        : BAUD;
 6    PARITY                          : T_UART_PARITY_MODE           := PARITY_NONE;
 7    PARITY_ERROR_HANDLING           : T_UART_PARITY_ERROR_HANDLING := PASSTHROUGH_ERROR_BYTE;
 8    PARITY_ERROR_IDENTIFIER         : std_logic_vector(7 downto 0) := 8x"0";
 9    ADD_INPUT_SYNCHRONIZERS         : boolean := TRUE;
10
11    -- Buffer Dimensioning
12    TX_MIN_DEPTH                    : positive          := 16;
13    TX_ESTATE_BITS                  : natural           := 0;
14    RX_MIN_DEPTH                    : positive          := 16;
15    RX_FSTATE_BITS                  : natural           := 0;
16
17    FLOWCTRL_XON_THRESHOLD          : real := 0.0625;
18    FLOWCTRL_XOFF_THRESHOLD         : real := 0.75;
19
20    -- Flow Control
21    FLOWCONTROL                     : T_IO_UART_FLOWCONTROL_KIND   := UART_FLOWCONTROL_NONE;
22    SWFC_XON_CHAR                   : std_logic_vector(7 downto 0) := x"11";  -- ^Q
23
24    SWFC_XOFF_CHAR                  : std_logic_vector(7 downto 0) := x"13"   -- ^S
25
26  );
27  port (
28    Clock               : in  std_logic;
29    Reset               : in  std_logic;
30
31    -- FIFO interface
32    TX_put              : in    std_logic;
33    TX_Data             : in    std_logic_vector(7 downto 0);
34    TX_Full             : out   std_logic;
35    TX_EmptyState       : out   std_logic_vector(imax(0, TX_ESTATE_BITS-1) downto 0);
36    TXFIFO_Reset        : in    std_logic;
37    TXFIFO_Empty        : out   std_logic;
38
39    RX_Valid            : out   std_logic;
40    RX_Data             : out   std_logic_vector(7 downto 0);
41    RX_got              : in    std_logic;
42    RX_FullState        : out   std_logic_vector(imax(0, RX_FSTATE_BITS-1) downto 0);
43    RX_Overflow         : out   std_logic;