PoC.sync.Vector

This module synchronizes a vector of bits from clock-domain Clock1 to clock-domain Clock2. The clock-domain boundary crossing is done by a change comparator, a T-FF, two synchronizer D-FFs and a reconstructive XOR indicating a value change on the input. This changed signal is used to capture the input for the new output. A busy flag is additionally calculated for the input clock domain.

Constraints:

This module uses sub modules which need to be constrained. Please attend to the notes of the instantiated sub modules.

Entity Declaration:

 1    INIT          : std_logic_vector    := x"00000000";             --
 2    SYNC_DEPTH    : T_MISC_SYNC_DEPTH   := T_MISC_SYNC_DEPTH'low    -- generate SYNC_DEPTH many stages, at least 2
 3  );
 4  port (
 5    Clock1        : in  std_logic;                                                  -- <Clock>  input clock
 6    Clock2        : in  std_logic;                                                  -- <Clock>  output clock
 7
 8    Input         : in  std_logic_vector((SLAVE_BITS + MASTER_BITS) - 1 downto 0);  -- @Clock1:  input vector
 9    Busy          : out std_logic;                                                  -- @Clock1:  busy bit
10    Strobe        : in  std_logic := '0';                                           -- @Clock1:  Transfer Strobe, only if MASTER_BITS=0
11
12    Output        : out std_logic_vector((SLAVE_BITS + MASTER_BITS) - 1 downto 0);  -- @Clock2:  output vector
13    Changed       : out  std_logic                                                  -- @Clock2:  changed bit
14  );
15end entity;