PoC.sync.Pulse

This module synchronizes multiple pulsed bits into the clock-domain Clock. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits are independent from each other. If a known vendor like Altera or Xilinx are recognized, a vendor specific implementation is chosen.

Attention

Use this synchronizer for very short signals (pulse).

Constraints:
General:

Please add constraints for meta stability to all ‘_meta’ signals and timing ignore constraints to all ‘_async’ signals.

Xilinx:

In case of a Xilinx device, this module will instantiate the optimized module PoC.xil.sync.Pulse. Please attend to the notes of sync_Bits.vhdl.

Altera sdc file:

TODO

Entity Declaration:

 1  );
 2  port (
 3    Clock         : in  std_logic;                                  -- <Clock>  output clock domain
 4    Input         : in  std_logic_vector(BITS - 1 downto 0);        -- @async:  input bits
 5    Output        : out std_logic_vector(BITS - 1 downto 0)         -- @Clock:  output bits
 6  );
 7end entity;
 8
 9
10architecture rtl of sync_Pulse is
11  constant DEV_INFO : T_DEVICE_INFO        := DEVICE_INFO;

See also

PoC.sync.Bits

For a common 2 D-FF synchronizer for flag-signals.

PoC.sync.Reset

For a special 2 D-FF synchronizer for reset-signals.

PoC.sync.Strobe

For a synchronizer for strobe-signals.

PoC.sync.Vector

For a multiple bits capable synchronizer.