PoC.sync.Bits

This module synchronizes multiple flag bits into clock-domain Clock. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits are independent from each other. If a known vendor like Altera or Xilinx are recognized, a vendor specific implementation is chosen.

Attention

Use this synchronizer only for long time stable signals (flags).

Constraints:
General:

Please add constraints for meta stability to all ‘_meta’ signals and timing ignore constraints to all ‘_async’ signals.

Xilinx:

In case of a Xilinx device, this module will instantiate the optimized module PoC.xil.sync.Bits. Please attend to the notes of sync_Bits.vhdl.

Altera sdc file:

TODO

Entity Declaration:

 1    INIT          : std_logic_vector    := x"00000000";             -- initialization bits
 2    SYNC_DEPTH    : T_MISC_SYNC_DEPTH   := T_MISC_SYNC_DEPTH'low;    -- generate SYNC_DEPTH many stages, at least 2
 3    FALSE_PATH      : boolean             := true;
 4    REGISTER_OUTPUT : boolean             := false
 5  );
 6  port (
 7    Clock         : in  std_logic;                                  -- <Clock>  output clock domain
 8    Input         : in  std_logic_vector(BITS - 1 downto 0);        -- @async:  input bits
 9    Output        : out std_logic_vector(BITS - 1 downto 0)         -- @Clock:  output bits
10  );
11end entity;

See also

PoC.sync.Reset

For a special 2 D-FF synchronizer for reset-signals.

PoC.sync.Pulse

For a special 1+2 D-FF synchronizer for pulse-signals.

PoC.sync.Strobe

For a synchronizer for strobe-signals.

PoC.sync.Vector

For a multiple bits capable synchronizer.