PoC.misc.gearbox.up_dc

This module provides a upscaling gearbox with a dependent clock (dc) interface. It perfoems a ‘byte’ to ‘word’ collection. The default order is LITTLE_ENDIAN (starting at byte(0)). Input “In_Data” is of clock domain “Clock1”; output “Out_Data” is of clock domain “Clock2”. The “In_Align” is required to mark the starting byte in the word. An optional input register can be added by enabling (ADD_INPUT_REGISTERS = TRUE).

Assertions:

  • Clock periods of Clock1 and Clock2 MUST be multiples of each other.

  • Clock1 and Clock2 MUST be phase aligned (related) to each other.

Entity Declaration:

 1    OUTPUT_BITS           : positive        := 32;                          -- output bit width
 2    ADD_INPUT_REGISTERS   : boolean         := FALSE                        -- add input register @Clock1
 3  );
 4  port (
 5    Clock1                : in  std_logic;                                  -- input clock domain
 6    Clock2                : in  std_logic;                                  -- output clock domain
 7    In_Align              : in  std_logic;                                  -- align word (one cycle high impulse)
 8    In_Data               : in  std_logic_vector(INPUT_BITS - 1 downto 0);  -- input word
 9    Out_Data              : out std_logic_vector(OUTPUT_BITS - 1 downto 0); -- output word
10    Out_Valid             : out std_logic                                   -- output is valid
11  );
12end entity;
13
14
15architecture rtl of gearbox_up_dc is
16  constant BIT_RATIO        : REAL      := real(OUTPUT_BITS) / real(INPUT_BITS);