PoC.misc.gearbox.down_cc

This module provides a downscaling gearbox with a common clock (cc) interface. It perfoems a ‘word’ to ‘byte’ splitting. The default order is LITTLE_ENDIAN (starting at byte(0)). Input “In_Data” and output “Out_Data” are of the same clock domain “Clock”. Optional input and output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE).

Entity Declaration:

 1    META_BITS             : natural   := 0;
 2    ADD_INPUT_REGISTERS   : boolean   := FALSE;
 3    ADD_OUTPUT_REGISTERS  : boolean   := FALSE
 4  );
 5  port (
 6    Clock       : in  std_logic;
 7
 8    In_Sync     : in  std_logic;
 9    In_Valid    : in  std_logic;
10    In_Next     : out std_logic;
11    In_Data     : in  std_logic_vector(INPUT_BITS - 1 downto 0);
12    In_Meta     : in  std_logic_vector(META_BITS - 1 downto 0);
13
14    Out_Sync    : out std_logic;
15    Out_Valid   : out std_logic;
16    Out_Data    : out std_logic_vector(OUTPUT_BITS - 1 downto 0);
17    Out_Meta    : out std_logic_vector(META_BITS - 1 downto 0);
18    Out_First   : out std_logic;
19    Out_Last    : out std_logic
20  );
21end entity;
22
23
24architecture rtl of gearbox_down_cc is
25  constant C_VERBOSE        : boolean     := FALSE;   --POC_VERBOSE;