PoC.misc.gearbox.down_cc

This module provides a downscaling gearbox with a common clock (cc) interface. It perfoems a ‘word’ to ‘byte’ splitting. The default order is LITTLE_ENDIAN (starting at byte(0)). Input “In_Data” and output “Out_Data” are of the same clock domain “Clock”. Optional input and output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE).

Entity Declaration:

 1  generic (
 2    INPUT_BITS            : positive  := 32;
 3    OUTPUT_BITS           : positive  := 24;
 4    META_BITS             : natural   := 0;
 5    ADD_INPUT_REGISTERS   : boolean   := FALSE;
 6    ADD_OUTPUT_REGISTERS  : boolean   := FALSE
 7  );
 8  port (
 9    Clock       : in  std_logic;
10
11    In_Sync     : in  std_logic;
12    In_Valid    : in  std_logic;
13    In_Next     : out std_logic;
14    In_Data     : in  std_logic_vector(INPUT_BITS - 1 downto 0);
15    In_Meta     : in  std_logic_vector(META_BITS - 1 downto 0);
16
17    Out_Sync    : out std_logic;
18    Out_Valid   : out std_logic;
19    Out_Data    : out std_logic_vector(OUTPUT_BITS - 1 downto 0);
20    Out_Meta    : out std_logic_vector(META_BITS - 1 downto 0);
21    Out_First   : out std_logic;
22    Out_Last    : out std_logic
23  );
24end entity;