PoC.misc.gearbox.down_dc

This module provides a downscaling gearbox with a dependent clock (dc) interface. It perfoems a ‘word’ to ‘byte’ splitting. The default order is LITTLE_ENDIAN (starting at byte(0)). Input “In_Data” is of clock domain “Clock1”; output “Out_Data” is of clock domain “Clock2”. Optional input and output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE).

Assertions:

  • Clock periods of Clock1 and Clock2 MUST be multiples of each other.

  • Clock1 and Clock2 MUST be phase aligned (related) to each other.

Entity Declaration:

 1    OUTPUT_ORDER          : T_BIT_ORDER     := LSB_FIRST;                   -- LSB_FIRST: start at byte(0), MSB_FIRST: start at byte(n-1)
 2    ADD_INPUT_REGISTERS   : boolean         := FALSE;                       -- add input register @Clock1
 3    ADD_OUTPUT_REGISTERS  : boolean         := FALSE                        -- add output register @Clock2
 4  );
 5  port (
 6    Clock1                : in  std_logic;                                  -- input clock domain
 7    Clock2                : in  std_logic;                                  -- output clock domain
 8    In_Data               : in  std_logic_vector(INPUT_BITS - 1 downto 0);  -- input word
 9    Out_Data              : out std_logic_vector(OUTPUT_BITS - 1 downto 0)  -- output word
10  );
11end entity;
12
13
14architecture rtl of gearbox_down_dc is
15  constant BIT_RATIO    : REAL      := real(INPUT_BITS) / real(OUTPUT_BITS);