AXI4Lite_UART

Based on axi4lite_Register, PoC.io.uart.fifo

Instantiation

Todo

needs documentation

UART : entity PoC.AXI4Lite_UART
generic map (
   CLOCK_FREQ => 100 MHz,
   BAUDRATE   => 115.200 kBd
)
port map (
  Clock        => Clock,
  Reset        => Reset,

  AXI4Lite_m2s => AXI4Lite_m2s,
  AXI4Lite_s2m => AXI4Lite_s2m,
  Config_irq   => Config_irq,

  UART_TX      => UART_TX,
  UART_RX      => UART_RX,
  UART_RTS     => UART_RTS,
  UART_CTS     => UART_CTS
);

Interface

Generics

CLOCK_FREQ

Name:

CLOCK_FREQ

Type:

FREQ

Default Value:

— — — —

Description:

Frequency of input clock.

BAUDRATE

Name:

BAUDRATE

Type:

BAUD

Default Value:

115.200 kBd

Description:

tbd

PARITY

Name:

PARITY

Type:

T_UART_PARITY_MODE

Default Value:

PARITY_NONE

Description:

PARITY_EVEN, PARITY_ODD, PARITY_NONE

PARITY_ERROR_HANDLING

Name:

PARITY_ERROR_HANDLING

Type:

T_UART_PARITY_ERROR_HANDLING

Default Value:

PASSTHROUGH_ERROR_BYTE

Description:

PASSTHROUGH_ERROR_BYTE, REPLACE_ERROR_BYTE, DROP_ERROR_BYTE

PARITY_ERROR_IDENTIFIER

Name:

PARITY_ERROR_IDENTIFIER

Type:

std_logic_vector(7 downto 0)

Default Value:

x"15"

Description:

tbd

ADD_INPUT_SYNCHRONIZERS

Name:

ADD_INPUT_SYNCHRONIZERS

Type:

boolean

Default Value:

TRUE

Description:

tbd

TX_FIFO_DEPTH

Name:

TX_FIFO_DEPTH

Type:

positive

Default Value:

16

Description:

tbd*

RX_FIFO_DEPTH

Name:

RX_FIFO_DEPTH

Type:

positive

Default Value:

16

Description:

tbd

FLOWCONTROL

Name:

FLOWCONTROL

Type:

T_IO_UART_FLOWCONTROL_KIND

Default Value:

UART_FLOWCONTROL_NONE

Description:

tbd

SWFC_XON_CHAR

Name:

SWFC_XON_CHAR

Type:

std_logic_vector(7 downto 0)

Default Value:

x"11"

Description:

tbd

SWFC_XOFF_CHAR

Name:

SWFC_XOFF_CHAR

Type:

std_logic_vector(7 downto 0)

Default Value:

x"13"

Description:

tbd

Ports

Clock

Name:

Clock

Type:

std_logic

Mode:

in

Default Value:

— — — —

Description:

Clock

Reset

Name:

Reset

Type:

std_logic

Mode:

in

Default Value:

— — — —

Description:

synchronous high-active reset

AXI4Lite_m2s

Name:

AXI4Lite_m2s

Type:

axi4lite.T_AXI4Lite_Bus_m2s

Mode:

in

Default Value:

— — — —

Description:

AXI4-Lite manager to subordinate signals.

AXI4Lite_s2m

Name:

AXI4Lite_s2m

Type:

axi4lite.T_AXI4Lite_Bus_s2m

Mode:

out

Default Value:

— — — —

Description:

AXI4-Lite subordinate to manager signals.

Config_irq

Name:

Config_irq

Type:

std_logic

Mode:

out

Default Value:

— — — —

Description:

AXI4-Lite subordinate to manager signals.

UART_TX

Name:

UART_TX

Type:

std_logic

Mode:

out

Default Value:

— — — —

Description:

tbd.

UART_RX

Name:

UART_RX

Type:

std_logic

Mode:

in

Default Value:

— — — —

Description:

tbd.

UART_RTS

Name:

UART_RTS

Type:

std_logic

Mode:

out

Default Value:

— — — —

Description:

tbd.

UART_CTS

Name:

UART_CTS

Type:

std_logic

Mode:

in

Default Value:

— — — —

Description:

tbd.

Configuration

User defined Word

Todo

tbd

Register Map

Offset

R/W Config

Default

Name

Description

0x0000

ReadOnly_NotRegistered

x"00000000"

Rx

Read from receive buffer.

0x0004

ReadWrite_NotRegistered

x"00000000"

Tx

Write into transmit buffer.

0x0008

ReadOnly

x"00000000"

Status

Receive status.

0x000C

ReadWrite

x"00000000"

Control

Command byte