AXI4Lite_Ocram_Adapter
Instantiation
Todo
needs documentation
Ocram_Adapter : entity PoC.AXI4Lite_Ocram_Adapter
generic map (
OCRAM_ADDRESS_BITS => 10,
OCRAM_DATA_BITS => 32
) port map (
Clock => Clock,
Reset => Reset,
AXI4Lite_m2s => AXI4Lite_m2s,
AXI4Lite_s2m => AXI4Lite_s2m,
Write_En => Write_En,
Address => Address,
Data_In => Data_In,
Data_Out => Data_Out
);
Interface
Generics
OCRAM_ADDRESS_BITS
- Name:
OCRAM_ADDRESS_BITS
- Type:
positive- Default Value:
— — — —
- Description:
tbd
OCRAM_DATA_BITS
- Name:
OCRAM_DATA_BITS
- Type:
positive- Default Value:
— — — —
- Description:
tbd
PREFFERED_READ_ACCESS
- Name:
PREFFERED_READ_ACCESS
- Type:
boolean- Default Value:
TRUE
- Description:
tbd
Ports
Clock
- Name:
Clock
- Type:
std_logic- Mode:
in
- Default Value:
— — — —
- Description:
Clock
Reset
- Name:
:port:``Reset`
- Type:
std_logic- Mode:
in
- Default Value:
— — — —
- Description:
synchronous high-active reset
AXI4Lite_M2S
- Name:
AXI4Lite_M2S
- Type:
axi4lite.T_AXI4Lite_Bus_m2s- Mode:
in
- Default Value:
— — — —
- Description:
AXI4-Lite manager to subordinate signals.
AXI4Lite_s2m
- Name:
AXI4Lite_s2m
- Type:
axi4lite.T_AXI4Lite_Bus_s2m- Mode:
out
- Default Value:
— — — —
- Description:
AXI4-Lite subordinate to manager signals.
Write_En
- Name:
Write_En
- Type:
std_logic- Mode:
out
- Default Value:
— — — —
- Description:
Write enable.
Address
- Name:
Address
- Type:
unsigned(OCRAM_ADDRESS_BITS-1 downto 0)- Mode:
out
- Default Value:
— — — —
- Description:
tbd
Data_In
- Name:
Data_In
- Type:
unsigned(OCRAM_ADDRESS_BITS-1 downto 0)- Mode:
in
- Default Value:
— — — —
- Description:
tbd
Data_Out
- Name:
Data_Out
- Type:
unsigned(OCRAM_ADDRESS_BITS-1 downto 0)- Mode:
out
- Default Value:
— — — —
- Description:
tbd
Configuration
User defined Word
Todo
tbd