PoC.arith.Same

This circuit may, for instance, be used to detect the first sign change and, thus, the range of a two’s complement number.

These components may be chained by using the output of the predecessor as guard input. This chaining allows to have intermediate results available while still ensuring the use of a fast carry chain on supporting FPGA architectures. When chaining, make sure to overlap both vector slices by one bit position as to avoid an undetected sign change between the slices.

Entity Declaration:

 1  port (
 2    g : in  std_logic := '1';                -- Guard Input (!g => !y)
 3    x : in  std_logic_vector(BITS-1 downto 0);  -- Input Vector
 4    y : out std_logic                        -- All-same Output
 5  );
 6end entity;
 7
 8
 9architecture rtl of arith_Same is
10  constant DEV_INFO  : T_DEVICE_INFO    := DEVICE_INFO;