PoC.arith.PRNG

This module implementes a Pseudo-Random Number Generator (PRNG) with configurable bit count (BITS). This module uses an internal list of FPGA optimized polynomials from 3 to 168 bits. The polynomials have at most 5 tap positions, so that long shift registers can be inferred instead of single flip-flops.

The generated number sequence includes the value all-zeros, but not all-ones.

Entity Declaration:

 1  generic (
 2    BITS : positive;
 3    SEED : std_logic_vector := "0"
 4  );
 5  port (
 6    Clock        : in  std_logic;
 7    Reset        : in  std_logic; -- reset value to seed
 8
 9    InitialValue : in  std_logic_vector := SEED; -- Is loaded when Reset = '1'
10    Got          : in  std_logic; -- the current value has been got, and a new value should be calculated
11    Value        : out std_logic_vector(BITS - 1 downto 0) -- the pseudo-random number
12  );