PoC.arith.Adder_Wide

Implements wide addition providing several options all based on an adaptation of a carry-select approach.

References:

  • Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser: FPGA-Specific Arithmetic Optimizations of Short-Latency Adders, FPL 2011. -> ARCH: AAM, CAI, CCA -> SKIPPING: CCC

  • Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol: A Novel Modular Adder for One Thousand Bits and More Using Fast Carry Chains of Modern FPGAs, FPL 2014. -> ARCH: PAI -> SKIPPING: PPN_KS, PPN_BK

Entity Declaration:

 1entity arith_Adder_Wide is
 2  generic (
 3    BITS        : positive;                -- Operand Width
 4    BLOCKS      : positive;                -- Block Count
 5
 6    ARCH        : T_Adder_Architecture     := AAM;        -- Architecture
 7    BLOCKING    : T_Adder_BlockingScheme := DFLT;       -- Blocking Scheme
 8    SKIPPING    : T_Adder_CarrySkipScheme := CCC;        -- Carry Skip Scheme
 9    P_INCLUSIVE : boolean   := false       -- Use Inclusive Propagate, i.e. c^1
10  );
11  port (
12    A        : in  std_logic_vector(BITS-1 downto 0);
13    B        : in  std_logic_vector(BITS-1 downto 0);
14    CarryIn  : in  std_logic;
15
16    Sum      : out std_logic_vector(BITS-1 downto 0);
17    CarryOut : out std_logic
18  );