PoC.mem.sdram.ctrl_s3esk
Controller for Micron DDR-SDRAM on Spartan-3E Starter Kit Board.
SDRAM Device: MT46V32M16-6T
Configuration
Parameter |
Description |
|---|---|
CLK_PERIOD |
Clock period in nano seconds. All SDRAM timings are calculated for the device stated above. |
CL |
CAS latency, choose according to clock frequency. |
BL |
Burst length. Choose BL=2 for single cycle memory transactions as required for the PoC.Mem interface. |
Tested with: CLK_PERIOD = 10.0, CL=2, BL=2.
Operation
Command, address and write data are sampled with the rising edge of clk.
Read data is aligned with clk_fb90_n. Either process data in this clock
domain, or connect a FIFO to transfer data into another clock domain of your
choice. This FIFO should capable of storing at least one burst (size BL/2)
+ start of next burst (size 1).
Synchronous resets are used.
Entity Declaration:
1 generic (
2 CLK_PERIOD : real;
3 BL : positive);
4
5 port (
6 clk : in std_logic;
7 clk_n : in std_logic;
8 clk90 : in std_logic;
9 clk90_n : in std_logic;
10 rst : in std_logic;
11 rst90 : in std_logic;
12 rst180 : in std_logic;
13 rst270 : in std_logic;
14 clk_fb90 : in std_logic;
15 clk_fb90_n : in std_logic;
16 rst_fb90 : in std_logic;
17 rst_fb270 : in std_logic;
18
19 user_cmd_valid : in std_logic;
20 user_wdata_valid : in std_logic;
21 user_write : in std_logic;
22 user_addr : in std_logic_vector(24 downto 0);
23 user_wdata : in std_logic_vector(31 downto 0);
24 user_got_cmd : out std_logic;
25 user_got_wdata : out std_logic;
26 user_rdata : out std_logic_vector(31 downto 0);
27 user_rstb : out std_logic;
28
29 sd_ck_p : out std_logic;
30 sd_ck_n : out std_logic;
31 sd_cke : out std_logic;
32 sd_cs : out std_logic;
33 sd_ras : out std_logic;
34 sd_cas : out std_logic;
35 sd_we : out std_logic;
36 sd_ba : out std_logic_vector(1 downto 0);
37 sd_a : out std_logic_vector(12 downto 0);
38 sd_ldqs : out std_logic;
39 sd_udqs : out std_logic;
40 sd_dq : inout std_logic_vector(15 downto 0));
41
42end sdram_ctrl_s3esk;