PoC.mem.sdram.ctrl_de0

Complete controller for ISSI SDR-SDRAM for Altera DE0 Board.

SDRAM Device: IS42S16400F

Configuration

Parameter

Description

CLK_PERIOD

Clock period in nano seconds. All SDRAM timings are calculated for the device stated above.

CL

CAS latency, choose according to clock frequency.

BL

Burst length. Choose BL=1 for single cycle memory transactions as required for the PoC.Mem interface.

Tested with: CLK_PERIOD = 7.5 (133 MHz), CL=2, BL=1.

Operation

Command, address and write data is sampled with clk. Read data is also aligned with clk.

For description on clkout see sdram_ctrl_phy_de0.

Synchronous resets are used.

Entity Declaration:

 1    CL          : positive;
 2    BL          : positive);
 3
 4  port (
 5    clk        : in    std_logic;
 6    clkout     : in    std_logic;
 7    rst        : in    std_logic;
 8
 9    user_cmd_valid   : in  std_logic;
10    user_wdata_valid : in  std_logic;
11    user_write       : in  std_logic;
12    user_addr        : in  std_logic_vector(21 downto 0);
13    user_wdata       : in  std_logic_vector(15 downto 0);
14    user_got_cmd     : out std_logic;
15    user_got_wdata   : out std_logic;
16    user_rdata       : out std_logic_vector(15 downto 0);
17    user_rstb        : out std_logic;
18
19    sd_ck      : out   std_logic;
20    sd_cke     : out   std_logic;
21    sd_cs      : out   std_logic;
22    sd_ras     : out   std_logic;
23    sd_cas     : out   std_logic;
24    sd_we      : out   std_logic;
25    sd_ba      : out   std_logic_vector(1 downto 0);
26    sd_a       : out   std_logic_vector(11 downto 0);
27    sd_dq      : inout std_logic_vector(15 downto 0));
28
29end sdram_ctrl_de0;
30
31architecture rtl of sdram_ctrl_de0 is
32
33  --