PoC.mem.ocrom.dp

Inferring / instantiating dual-port read-only memory, with:

  • dual clock, clock enable,

  • 2 read ports.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

WARNING: The simulated behavior on RT-level is not correct.

TODO: add timing diagram TODO: implement correct behavior for RT-level simulation

Entity Declaration:

 1  port (
 2    clk1 : in std_logic;
 3    clk2 : in std_logic;
 4    ce1 : in  std_logic;
 5    ce2 : in  std_logic;
 6    a1   : in unsigned(A_BITS-1 downto 0);
 7    a2   : in unsigned(A_BITS-1 downto 0);
 8    q1   : out std_logic_vector(D_BITS-1 downto 0);
 9    q2   : out std_logic_vector(D_BITS-1 downto 0)
10  );
11end entity;
12
13
14architecture rtl of ocrom_dp is
15  constant DEPTH        : positive := 2**A_BITS;
16
17begin