PoC.mem.ocrom.dp

Inferring / instantiating dual-port read-only memory, with:

  • dual clock, clock enable,

  • 2 read ports.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

WARNING: The simulated behavior on RT-level is not correct.

TODO: add timing diagram TODO: implement correct behavior for RT-level simulation

Entity Declaration:

 1    D_BITS    : positive;
 2    FILENAME  : string    := ""
 3  );
 4  port (
 5    clk1 : in std_logic;
 6    clk2 : in std_logic;
 7    ce1 : in  std_logic;
 8    ce2 : in  std_logic;
 9    a1   : in unsigned(A_BITS-1 downto 0);
10    a2   : in unsigned(A_BITS-1 downto 0);
11    q1   : out std_logic_vector(D_BITS-1 downto 0);
12    q2   : out std_logic_vector(D_BITS-1 downto 0)
13  );
14end entity;
15
16
17architecture rtl of ocrom_dp is