PoC.io.ddrio.out

Instantiates chip-specific DDR output registers.

Both data DataOut_high/low as well as OutputEnable are sampled with the rising_edge(Clock) from the on-chip logic. DataOut_high is brought out with this rising edge. DataOut_low is brought out with the falling edge.

OutputEnable (Tri-State) is high-active. It is automatically inverted if necessary. If an output enable is not required, you may save some logic by setting NO_OUTPUT_ENABLE = true.

If NO_OUTPUT_ENABLE = false then output is disabled after power-up. If NO_OUTPUT_ENABLE = true then output after power-up equals INIT_VALUE.

Pad must be connected to a PAD because FPGAs only have these registers in IOBs.

Entity Declaration:

 1  generic (
 2    NO_OUTPUT_ENABLE    : boolean     := false;
 3    BITS                : positive;
 4    INIT_VALUE          : bit_vector  := x"FFFFFFFF"
 5  );
 6  port (
 7    Clock         : in  std_logic;
 8    ClockEnable   : in  std_logic := '1';
 9    OutputEnable  : in  std_logic := '1';
10    DataOut_high  : in  std_logic_vector(BITS - 1 downto 0);
11    DataOut_low   : in  std_logic_vector(BITS - 1 downto 0);
12    Pad           : out std_logic_vector(BITS - 1 downto 0)
13  );
14end entity;