PoC.cache.replacement_policy
Supported policies:
Abbr. |
Policies |
supported |
|---|---|---|
RR |
round robin |
not yet |
RAND |
random |
not yet |
CLOCK |
clock algorithm |
not yet |
LRU |
least recently used |
YES |
LFU |
least frequently used |
not yet |
Command thruth table:
TagAccess |
ReadWrite |
Invalidate |
Replace |
Command |
|---|---|---|---|---|
0 |
0 |
None |
||
1 |
0 |
0 |
0 |
TagHit and reading a cache line |
1 |
1 |
0 |
0 |
TagHit and writing a cache line |
1 |
0 |
1 |
0 |
TagHit and invalidate a cache line (while reading) |
1 |
1 |
1 |
0 |
TagHit and invalidate a cache line (while writing) |
0 |
0 |
1 |
Replace cache line |
In a set-associative cache, each cache-set has its own instance of this component.
The input HitWay specifies the accessed way in a fully-associative or
set-associative cache.
The output ReplaceWay identifies the way which will be replaced as next by
a replace command. In a set-associative cache, this is the way in a specific
cache set (see above).
Entity Declaration:
1 generic (
2 REPLACEMENT_POLICY : string := "LRU";
3 CACHE_WAYS : positive := 32
4 );
5 port (
6 Clock : in std_logic;
7 Reset : in std_logic;
8
9 -- replacement interface
10 Replace : in std_logic;
11 ReplaceWay : out std_logic_vector(log2ceilnz(CACHE_WAYS) - 1 downto 0);
12
13 -- cacheline usage update interface
14 TagAccess : in std_logic;
15 ReadWrite : in std_logic;
16 Invalidate : in std_logic;
17 HitWay : in std_logic_vector(log2ceilnz(CACHE_WAYS) - 1 downto 0)
18 );
19end entity;