PoC.cache.par2

Cache with parallel tag-unit and data memory. For the data memory, PoC.mem.ocram.sp is used.

Configuration

Parameter

Description

REPLACEMENT_POLICY

Replacement policy. For supported policies see PoC.cache_replacement_policy.

CACHE_LINES

Number of cache lines.

ASSOCIATIVITY

Associativity of the cache.

ADDR_BITS

Number of address bits. Each address identifies exactly one cache line in memory.

DATA_BITS

Size of a cache line in bits. DATA_BITS must be divisible by 8.

Command truth table

Request

ReadWrite

Invalidate

Replace

Command

0

0

0

0

None

1

0

0

0

Read cache line

1

1

0

0

Update cache line

1

0

1

0

Read cache line and discard it

1

1

1

0

Write cache line and discard it

0

0

0

1

Read cache line before replace.

0

1

0

1

Replace cache line.

Operation

All inputs are synchronous to the rising-edge of the clock clock.

All commands use Address to lookup (request) or replace a cache line. Address and OldAddress do not include the word/byte select part. Each command is completed within one clock cycle, but outputs are delayed as described below.

Upon requests, the outputs CacheMiss and CacheHit indicate (high-active) whether the Address is stored within the cache, or not. Both outputs have a latency of one clock cycle (pipelined) if HIT_MISS_REG is true, otherwise the result is outputted immediately (combinational).

Upon writing a cache line, the new content is given by CacheLineIn. Only the bytes which are not masked, i.e. the corresponding bit in WriteMask is ‘0’, are actually written.

Upon reading a cache line, the current content is outputed on CacheLineOut with a latency of one clock cycle.

Replacing a cache line requires two steps, both with Replace = '1':

  1. Read old contents of cache line by setting ReadWrite to ‘0’. The old content is outputed on CacheLineOut and the old tag on OldAddress, both with a latency of one clock cycle.

  2. Write new cache line by setting ReadWrite to ‘1’. The new content is given by CacheLineIn. All bytes shall be written, i.e. WriteMask = 0. The new cache line content will be outputed again on CacheLineOut in the next clock cycle (latency = 1).

Warning

If the design is synthesized with Xilinx ISE / XST, then the synthesis option “Keep Hierarchy” must be set to SOFT or TRUE.

Entity Declaration:

 1    ASSOCIATIVITY      : positive := 32;
 2    ADDR_BITS          : positive := 8;
 3    DATA_BITS          : positive := 8;
 4    HIT_MISS_REG       : boolean  := true  -- must be true for Cocotb.
 5  );
 6  port (
 7    Clock : in std_logic;
 8    Reset : in std_logic;
 9
10    Request    : in std_logic;
11    ReadWrite  : in std_logic;
12    WriteMask  : in std_logic_vector(DATA_BITS/8 - 1 downto 0) := (others => '0');
13    Invalidate : in std_logic;
14    Replace    : in std_logic;
15    Address    : in std_logic_vector(ADDR_BITS-1 downto 0);
16
17    CacheLineIn  : in  std_logic_vector(DATA_BITS - 1 downto 0);
18    CacheLineOut : out std_logic_vector(DATA_BITS - 1 downto 0);
19    CacheHit     : out std_logic := '0';
20    CacheMiss    : out std_logic := '0';
21    OldAddress   : out std_logic_vector(ADDR_BITS-1 downto 0)
22  );
23end entity;
24
25
26architecture rtl of cache_par2 is
27  attribute KEEP : boolean;