PoC.bus.stream.Mirror

Todo

No documentation available.

Entity Declaration:

 1    META_BITS   : positive_vector := (0 => 8);
 2    META_LENGTH : positive_vector := (0 => 16)
 3  );
 4  port (
 5    Clock : in  std_logic;
 6    Reset : in  std_logic;
 7    -- IN Port
 8    In_Valid     : in  std_logic;
 9    In_Data      : in  std_logic_vector(DATA_BITS - 1 downto 0);
10    In_SOF       : in  std_logic;
11    In_EOF       : in  std_logic;
12    In_Ack       : out std_logic;
13    In_Meta_rst  : out std_logic;
14    In_Meta_nxt  : out std_logic_vector(META_BITS'length - 1 downto 0);
15    In_Meta_Data : in  std_logic_vector(isum(META_BITS) - 1 downto 0);
16    -- OUT Port
17    Out_Valid     : out std_logic_vector(PORTS - 1 downto 0);
18    Out_Data      : out T_SLM(PORTS - 1 downto 0, DATA_BITS - 1 downto 0);
19    Out_SOF       : out std_logic_vector(PORTS - 1 downto 0);
20    Out_EOF       : out std_logic_vector(PORTS - 1 downto 0);
21    Out_Ack       : in  std_logic_vector(PORTS - 1 downto 0);
22    Out_Meta_rst  : in  std_logic_vector(PORTS - 1 downto 0);
23    Out_Meta_nxt  : in  T_SLM(PORTS - 1 downto 0, META_BITS'length - 1 downto 0);
24    Out_Meta_Data : out T_SLM(PORTS - 1 downto 0, isum(META_BITS) - 1 downto 0)
25  );
26end entity;
27architecture rtl of stream_Mirror is
28  signal FifoStage_put     : std_logic;
29  signal FifoStage_DataIn  : std_logic_vector(DATA_BITS + 1 downto 0);
30  signal FifoStage_Full    : std_logic;