PoC.bus.stream.FrameGenerator
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Entity Declaration:
1entity stream_FrameGenerator is
2 generic (
3 DATA_BITS : positive := 8;
4 WORD_BITS : positive := 16
5 );
6 port (
7 Clock : in std_logic;
8 Reset : in std_logic;
9 -- CSE interface
10 Command : in T_FRAMEGEN_COMMAND;
11 Status : out T_FRAMEGEN_STATUS;
12 -- Control interface
13 Sequences : in T_SLV_16;
14 FrameLength : in T_SLV_16;
15 -- OUT Port
16 Out_Valid : out std_logic;
17 Out_Data : out std_logic_vector(DATA_BITS - 1 downto 0);
18 Out_SOF : out std_logic;
19 Out_EOF : out std_logic;
20 Out_Ack : in std_logic
21 );
22end entity;
23
24
25architecture rtl of stream_FrameGenerator is
26 constant N_arith : natural := integer((real(DATA_BITS) / 168.0) +0.5);--(DATA_BITS + 83) / 168;integer(real(DATA_BITS9 / 168.0) +0.5);