PoC.misc.gearbox.up_cc

This module provides a downscaling gearbox with a common clock (cc) interface. It perfoems a ‘byte’ to ‘word’ collection. The default order is LITTLE_ENDIAN (starting at byte(0)). Input “In_Data” and output “Out_Data” are of the same clock domain “Clock”. Optional input and output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE).

Entity Declaration:

 1    META_BITS              : natural    := 0;
 2    ADD_INPUT_REGISTERS    : boolean    := FALSE;
 3    ADD_OUTPUT_REGISTERS  : boolean    := FALSE
 4  );
 5  port (
 6    Clock        : in  std_logic;
 7
 8    In_Sync      : in  std_logic;
 9    In_Valid    : in  std_logic;
10    In_Data      : in  std_logic_vector(INPUT_BITS - 1 downto 0);
11    In_Meta      : in  std_logic_vector(META_BITS - 1 downto 0);
12
13    Out_Sync    : out std_logic;
14    Out_Valid    : out std_logic;
15    Out_Data    : out std_logic_vector(OUTPUT_BITS - 1 downto 0);
16    Out_Meta    : out std_logic_vector(META_BITS - 1 downto 0);
17    Out_First    : out std_logic;
18    Out_Last    : out std_logic
19  );
20end entity;
21
22
23architecture rtl of gearbox_Up_cc is
24  constant C_VERBOSE        : boolean      := FALSE;  --POC_VERBOSE;