PoC.mem.ocrom.DualPort

Inferring / instantiating dual-port read-only memory, with:

  • dual clock, clock enable,

  • 2 read ports.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

WARNING: The simulated behavior on RT-level is not correct.

TODO: add timing diagram TODO: implement correct behavior for RT-level simulation

Entity Declaration:

 1  );
 2  port (
 3    PortA_Clock       : in  std_logic;
 4    PortA_ClockEnable : in  std_logic;
 5    PortA_Address     : in  unsigned(ADDRESS_BITS-1 downto 0);
 6    PortA_DataOut     : out std_logic_vector(DATA_BITS-1 downto 0);
 7
 8    PortB_Clock       : in  std_logic;
 9    PortB_ClockEnable : in  std_logic;
10    PortB_Address     : in  unsigned(ADDRESS_BITS-1 downto 0);
11    PortB_DataOut     : out std_logic_vector(DATA_BITS-1 downto 0)
12  );
13end entity;
14
15
16architecture rtl of ocrom_DualPort is
17  constant WORDS        : positive := 2**ADDRESS_BITS;