PoC.mem.ocram.TrueDualPort_Simulation

Simulation model for true dual-port memory, with:

  • dual clock, clock enable,

  • 2 read/write ports.

The interface matches that of the IP core PoC.mem.ocram.tdp. But the implementation there is restricted to the description supported by various synthesis compilers. The implementation here also simulates the correct Mixed-Port Read-During-Write Behavior and handles X propagation.

Entity Declaration:

 1    FILENAME     : string    := ""                        -- file-name for RAM initialization
 2  );
 3  port (
 4    PortA_Clock       : in  std_logic;                               -- clock for 1st port
 5    PortA_ClockEnable : in  std_logic;                               -- clock-enable for 1st port
 6    PortA_WriteEnable : in  std_logic;                               -- write-enable for 1st port
 7    PortA_Address     : in  unsigned(ADDRESS_BITS-1 downto 0);       -- address for 1st port
 8    PortA_DataIn      : in  std_logic_vector(DATA_BITS-1 downto 0);  -- write-data for 1st port
 9    PortA_DataOut     : out std_logic_vector(DATA_BITS-1 downto 0);  -- read-data from 1st port
10
11    PortB_Clock       : in  std_logic;                               -- clock for 2nd port
12    PortB_ClockEnable : in  std_logic;                               -- clock-enable for 2nd port
13    PortB_WriteEnable : in  std_logic;                               -- write-enable for 2nd port
14    PortB_Address     : in  unsigned(ADDRESS_BITS-1 downto 0);       -- address for 2nd port
15    PortB_DataIn      : in  std_logic_vector(DATA_BITS-1 downto 0);  -- write-data for 2nd port
16    PortB_DataOut     : out std_logic_vector(DATA_BITS-1 downto 0)   -- read-data from 2nd port
17  );
18end entity;
19
20
21architecture sim of ocram_TrueDualPort_Simulation is