PoC.mem.ocram.TrueDualPort

Inferring / instantiating true dual-port memory, with:

  • dual clock, clock enable,

  • 2 read/write ports.

Command truth table for port 1, same applies to port 2:

ce1

we1

Command

0

X

No operation

1

0

Read from memory

1

1

Write to memory

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

Same-Port Read-During-Write

When writing data through port 1, the read output of the same port (q1) will output the new data (d1, in the following clock cycle) which is aka. “write-first behavior”.

Same applies to port 2.

Mixed-Port Read-During-Write

When reading at the write address, the read value will be unknown which is aka. “don’t care behavior”. This applies to all reads (at the same address) which are issued during the write-cycle time, which starts at the rising-edge of the write clock and (in the worst case) extends until the next rising-edge of that write clock.

For simulation, always our dedicated simulation model IP/ocram_TrueDualPort_sim is used.

Entity Declaration:

 1    ADDRESS_BITS : positive;                              -- number of address bits
 2    DATA_BITS    : positive;                              -- number of data bits
 3    FILENAME     : string    := ""                        -- file-name for RAM initialization
 4  );
 5  port (
 6    PortA_Clock       : in  std_logic;                               -- clock for 1st port
 7    PortA_ClockEnable : in  std_logic;                               -- clock-enable for 1st port
 8    PortA_WriteEnable : in  std_logic;                               -- write-enable for 1st port
 9    PortA_Address     : in  unsigned(ADDRESS_BITS-1 downto 0);       -- address for 1st port
10    PortA_DataIn      : in  std_logic_vector(DATA_BITS-1 downto 0);  -- write-data for 1st port
11    PortA_DataOut     : out std_logic_vector(DATA_BITS-1 downto 0);  -- read-data from 1st port
12
13    PortB_Clock       : in  std_logic;                               -- clock for 2nd port
14    PortB_ClockEnable : in  std_logic;                               -- clock-enable for 2nd port
15    PortB_WriteEnable : in  std_logic;                               -- write-enable for 2nd port
16    PortB_Address     : in  unsigned(ADDRESS_BITS-1 downto 0);       -- address for 2nd port
17    PortB_DataIn      : in  std_logic_vector(DATA_BITS-1 downto 0);  -- write-data for 2nd port
18    PortB_DataOut     : out std_logic_vector(DATA_BITS-1 downto 0)   -- read-data from 2nd port
19  );
20end entity;