PoC.mem.ocram.SimpleDualPort_WriteFirst

Inferring / instantiating simple dual-port memory, with:

  • single clock, clock enable,

  • 1 read port plus 1 write port.

Command truth table:

ce

we

Command

0

X

No operation

1

0

Read only from memory

1

1

Read from and Write to memory

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

Mixed-Port Read-During-Write

When reading at the write address, the read value will be the new data, aka. “write-first behavior”. Of course, the read is still synchronous, i.e, the latency is still one clock cyle.

Entity Declaration:

 1-- XXX: why is this not a mode to ocram_SimpleDualPort?
 2entity ocram_SimpleDualPort_WriteFirst is
 3  generic (
 4    ADDRESS_BITS : positive;                           -- number of address bits
 5    DATA_BITS    : positive;                           -- number of data bits
 6    FILENAME     : string    := ""                     -- file-name for RAM initialization
 7  );
 8  port (
 9    Clock         : in  std_logic;                               -- clock
10    ClockEnable   : in  std_logic;                               -- clock-enable
11
12    Write_Enable  : in  std_logic;                               -- write enable
13    Write_Address : in  unsigned(ADDRESS_BITS-1 downto 0);       -- write address
14    Write_DataIn  : in  std_logic_vector(DATA_BITS-1 downto 0);  -- data in
15
16    Read_Address  : in  unsigned(ADDRESS_BITS-1 downto 0);       -- read address