PoC.mem.lut.Sine
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Entity Declaration:
1 MAX_AMPLITUDE : positive := 255;
2 POINTS : positive := 4096;
3 OFFSET_DEG : REAL := 0.0;
4 QUARTERS : positive := 4
5 );
6 port (
7 Clock : in std_logic;
8 Input : in std_logic_vector(log2ceilnz(POINTS) - 1 downto 0);
9 Output : out std_logic_vector(log2ceilnz(MAX_AMPLITUDE + ((QUARTERS - 1) / 2)) downto 0)
10 );
11end entity;
12
13
14architecture rtl of lut_Sine is