PoC.mem.lut.Sine
Todo
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Entity Declaration:
1 OFFSET_DEG : REAL := 0.0;
2 QUARTERS : positive := 4
3 );
4 port (
5 Clock : in std_logic;
6 Input : in std_logic_vector(log2ceilnz(POINTS) - 1 downto 0); -- XXX: unsigned (offset?)
7 Output : out std_logic_vector(log2ceilnz(MAX_AMPLITUDE + ((QUARTERS - 1) / 2)) downto 0) -- XXX: unsigned (negative?)
8 );
9end entity;
10
11architecture rtl of lut_Sine is
12 signal Output_nxt : std_logic_vector(Output'range);
13begin
14 -- ===========================================================================