PoC.mem.ddr3.mem2mig_adapter_Series7

Adapter between the PoC.Mem interface and the application interface (“app”) of the Xilinx MIG IP core for 7-Series FPGAs.

Simplifies the application interface (“app”) of the Xilinx MIG IP core. The PoC.Mem interface provides single-cycle fully pipelined read/write access to the memory. All accesses are word-aligned. Always all bytes of a word are written to the memory. More details can be found here.

Generic parameters:

  • D_BITS: Data bus width of the PoC.Mem and “app” interface. Also size of one word in bits.

  • DQ_BITS: Size of data bus between memory controller and external memory (DIMM, SoDIMM).

  • MEM_A_BITS: Address bus width of the PoC.Mem interface.

  • APP_A_BTIS: Address bus width of the “app” interface.

Containts only combinational logic.

Entity Declaration:

 1  generic (
 2    D_BITS     : positive;
 3    DQ_BITS    : positive;
 4    MEM_A_BITS : positive;
 5    APP_A_BITS : positive
 6  );
 7
 8  port (
 9    -- PoC.Mem interface
10    mem_req   : in  std_logic;
11    mem_write : in  std_logic;
12    mem_addr  : in  unsigned(MEM_A_BITS-1 downto 0);
13    mem_wdata : in  std_logic_vector(D_BITS-1 downto 0);
14    mem_wmask : in  std_logic_vector(D_BITS/8-1 downto 0) := (others => '0');
15    mem_rdy   : out std_logic;
16    mem_rstb  : out std_logic;
17    mem_rdata : out std_logic_vector(D_BITS-1 downto 0);
18
19    -- Xilinx MIG IP Core interface
20    init_calib_complete : in  std_logic;
21    app_rd_data         : in  std_logic_vector((D_BITS)-1 downto 0);
22    app_rd_data_end     : in  std_logic;
23    app_rd_data_valid   : in  std_logic;
24    app_rdy             : in  std_logic;
25    app_wdf_rdy         : in  std_logic;
26    app_addr            : out std_logic_vector(APP_A_BITS-1 downto 0);
27    app_cmd             : out std_logic_vector(2 downto 0);
28    app_en              : out std_logic;
29    app_wdf_data        : out std_logic_vector((D_BITS)-1 downto 0);
30    app_wdf_end         : out std_logic;
31    app_wdf_mask        : out std_logic_vector((D_BITS)/8-1 downto 0);
32    app_wdf_wren        : out std_logic
33  );
34
35end entity ddr3_mem2mig_adapter_Series7;