.. _IP:misc_WordAligner:

WordAligner
###########

.. TODO:: No documentation available.


.. rubric:: Entity Declaration:

.. literalinclude:: ../../../src/misc/misc_WordAligner.vhdl
   :language: vhdl
   :tab-width: 2
   :linenos:
   :lines: 39-52

Source file: `misc/misc_WordAligner.vhdl <https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc_WordAligner.vhdl>`_