.. _IP/ocrom_SinglePort:

PoC.mem.ocrom.SinglePort
########################

.. only:: html

   .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png
               :scale: 40
               :target: https://github.com/VHDL/PoC/blob/main/src/mem/ocrom/ocrom_SinglePort.vhdl
               :alt: Source Code on GitHub
   .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png
               :scale: 40
               :target: https://github.com/VHDL/PoC/blob/main/tb/mem/ocrom/ocrom_SinglePort_tb.vhdl
               :alt: Source Code on GitHub

   .. sidebar:: GitHub Links

      * |gh-src| :pocsrc:`Sourcecode <mem/ocrom/ocrom_SinglePort.vhdl>`
      * |gh-tb| :poctb:`Testbench <mem/ocrom/ocrom_SinglePort_tb.vhdl>`

Inferring / instantiating single-port read-only memory

- single clock, clock enable
- 1 read port




.. rubric:: Entity Declaration:

.. literalinclude:: ../../../../src/mem/ocrom/ocrom_SinglePort.vhdl
   :language: vhdl
   :tab-width: 2
   :linenos:
   :lines: 53-65



.. only:: latex

   Source file: :pocsrc:`mem/ocrom/ocrom_SinglePort.vhdl <mem/ocrom/ocrom_SinglePort.vhdl>`