.. _IP:stream_Mux:

PoC.bus.stream.Mux
##################

.. only:: html

   .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png
               :scale: 40
               :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream_Mux.vhdl
               :alt: Source Code on GitHub
   .. |gh-tb| image:: /_static/logos/GitHub-Mark-32px.png
               :scale: 40
               :target: https://github.com/VLSI-EDA/PoC/blob/master/tb/bus/stream/stream_Mux_tb.vhdl
               :alt: Source Code on GitHub

   .. sidebar:: GitHub Links

      * |gh-src| :pocsrc:`Sourcecode <bus/stream/stream_Mux.vhdl>`
      * |gh-tb| :poctb:`Testbench <bus/stream/stream_Mux_tb.vhdl>`

.. TODO:: No documentation available.



.. rubric:: Entity Declaration:

.. literalinclude:: ../../../../src/bus/stream/stream_Mux.vhdl
   :language: vhdl
   :tab-width: 2
   :linenos:
   :lines: 41-69



.. only:: latex

   Source file: :pocsrc:`bus/stream/stream_Mux.vhdl <bus/stream/stream_Mux.vhdl>`